1. Field of the Invention
The present invention relates generally to an adder and more specifically to a high-speed carry adder of a relatively simple circuit configuration.
2. Description of the Prior Art
Conventionally, a carry adder of Manchester type has been well known, which comprises a plurality of full adder for each generating a carry signal or transmitting a carry signal from a less significant bit to a more significant bit, in spite of a relatively simple circuit configuration.
A carry is transmitted from a less significant bit to a more significant bit through a plurality of series-connected pass transistors. Therefore, the carry transmission time is subjected to the influence of the turn-on resistances and stray capacitances of the pass transistors. As a result, when the number of series-connected pass transistors increases, the carry transmission speed is reduced.
To overcome this problem, a skip circuit is usually connected across the full adders in a block to skip a carry over the series-connected pass transistors. However, since the turn-on resistances of and the stray capacitances of the pass transistors are still connected to the output of the skip circuit as a load, the carry transmission speed is subjected to the influence of the potential level of a carry to be transmitted and the potential level of the stray capacitances of the pass transistors, thus resulting in a problem such that it is impossible to transmit a carry signal at high constant speed from a full adder of the preceding less significant bit block to a full adder of the succeeding more significant bit block, irrespective of the potential levels of the carry and the stray capacitance of the pass transistors which constitute the carry adder.
A more detailed description of the prior-art carry adder of Manchester type will be made hereinafter with reference to the attached drawings under DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS.